SPI1 user register.
| SPI_MEM_CK_OUT_EDGE | the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. |
| SPI_MEM_FWRITE_DUAL | In the write operations read-data phase apply 2 signals |
| SPI_MEM_FWRITE_QUAD | In the write operations read-data phase apply 4 signals |
| SPI_MEM_FWRITE_DIO | In the write operations address phase and read-data phase apply 2 signals. |
| SPI_MEM_FWRITE_QIO | In the write operations address phase and read-data phase apply 4 signals. |
| SPI_MEM_USR_MISO_HIGHPART | read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. |
| SPI_MEM_USR_MOSI_HIGHPART | write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. |
| SPI_MEM_USR_DUMMY_IDLE | SPI clock is disable in dummy phase when the bit is enable. |
| SPI_MEM_USR_MOSI | This bit enable the write-data phase of an operation. |
| SPI_MEM_USR_MISO | This bit enable the read-data phase of an operation. |
| SPI_MEM_USR_DUMMY | This bit enable the dummy phase of an operation. |
| SPI_MEM_USR_ADDR | This bit enable the address phase of an operation. |
| SPI_MEM_USR_COMMAND | This bit enable the command phase of an operation. |